Self Con guring Binary Multipliers for LUT addressable FPGAs

In this paper we present a self con gurable multiplication technique allowing vari able con guration time for a class of LUT based Field Programmable Gate Arrays FPGAs which exist today We show this technique to be implementable on FPGA architectures allowing internally addressable RAM primitives to be directly mapped to the Logic Elements LEs of the logic resource This provides run time read write ad dressing capabilities to the FPGA logic elements which in turn is viewed as an FPGA possessing a run time recon gurable logic resource As an emerging eld of computing research recon gurable computing provides an area time tradeo that is actively in vestigated by many researchers We base the variable parameter for our multiplier on the recon guration time required and present results showing the e ective area time performance for multipliers of varying input bit size Results indicate the achiev able increase in functional density for multiplication on FPGAs implemented utilising recon guration Introduction FPGAs provide a con gurable logic platform on which digital designs can be implemented Conventionally designs are implemented by a process of design entry interaction with a CAD tool which performs the required logic synthesis placement and routing necessary to generate the design con guration the FPGA will take The process of synthesis takes the input logic function and functionally decomposes it to t into the computing elements LEs distributed throughout the FPGA in a two dimensional nature of the FPGA The result is a set of nodes which must be placed within the FPGA and an interconnection require ment between these nodes that must be realised by the FPGA interconnection resource The process of placement and routing performs this task and produces the con guration for the FPGA that must be loaded to allow the input logic function to be performed The con guration information can be viewed to consist of two parts a logic con guration